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VLSI Gate Sizing

VLSI gate and transistor sizing is a critical step of designing high-performance digital chip designs. In this article I will explain why it is necessary, and how it should be done to achieve an optimal tradeoff between area and performance.

Intro to VLSI Transistors

CMOS gates are built by stacking a pull-up network of PMOS transistors above a pull-down network of NMOS transistors. The size of the transistors can vary, restricted only by a "minimum size" that a transistor can have, which depends on the process node. Minimum size transistors provide the highest resistance transistors in any given process node, since they have the lowest W/L ratio. Therefore we can label the resistance of these transistors as "R", whereas the resistance of wider transistors can be referred to as "R/2", "R/3", etc. The mobility of electrons is roughly double that of holes, so a minimum size PMOS transistor will have roughly double the resistance of a minimum size NMOS transistor. Therefore minimum size PMOS transistors will have a resistance of "2R".

The Problem

Shown below is the simplest circuit in the CMOS logic family, an inverter. Assume that the PMOS and NMOS are both minimum size, 1 width transistors. Since the mobility of electrons is double that of holes, the resistance of the PMOS is double that of the NMOS. If we say that the NMOS has resistance R, the PMOS will have resistance 2R. Since digital circuits must meet timing 100% of the time, they are ruled by their worst case. This means that we will have to characterize this inverter as having a delay of 2*RC, even though it will switch faster when pulling down. This is a waste of the speed of the pull-down network, and we can do better.

The Solution

If we instead size the PMOS to be double the width of the NMOS, the pull-up resistance is now also R. This makes the pull-up and pull-down networks equally fast, giving the gate a total delay of only 1*RC.

Image 1

Minimum-sized inverter

Image 2

Equally-timed inverter

NOTE
The gate is now twice as fast, but it came at the cost of increasing the size of the PMOS transistor. This has two negative effects; it increases the area of the circuit, and increases the load capacitance of the previous gate. This tradeoff is almost always worth it because in a real layout the increase in area will be marginal at worst, and we sped up the output by 2x whilst only slowing the input by 33%.

Extending to a NAND Gate

Shown below is a NAND gate. It is constructed by connecting the pull-up network in parallel, and the pull-down network in series. It only takes one PMOS transistor to be on for the output to be pulled high, whereas all of the NMOS transistors must be on in order for the output to be pulled low. When the gate decides to toggle its output, some RC delay is incurred as the capacitance C of the output has to be charged through the transistors, which have some resistance R.

Image 1

A NAND gate in CMOS

Image 2

A properly sized NAND gate

So we have now built a NAND gate, right?

Yes, but since a minimum-sized NAND gate would also be the equally-timed, why would we not prefer a minimum-sized NAND gate?